The present invention relates to the fabrication of integrated circuits. More particularly, the invention provides a technique, including a method and apparatus, for forming improved tungsten silicide (WSi.sub.x) films.
As advances in integrated circuit technology lead to a scaling down of device dimensions and an increase in chip size and complexity, closely spaced interconnection lines that have smaller cross-sectional areas than lines previous used are required. The small cross-sectional area of these interconnection lines results in increased generation of resistive heat, while the close spacing of the lines results in less heat dissipation. This combination of more resistive heat generation and less heat dissipation can cause high temperatures which can result in part failure. Also, the higher resistivity increases the RC time constant and thus affects the delay time of the circuit. Low delay times are desirable for high speed circuits.
To overcome this problem, refractory metal silicide films having lower resistivities than polysilicon films were developed for use in these improved integrated circuits. Such metal silicide films result in circuits having lower delay times and less heat generation within the circuit. For gate metallizations, a low resistivity tungsten silicide film is deposited on top of a layer of polycrystalline silicon (polysilicon), to form a layered structure called a "polycide" structure. Two examples of such polycide structures are shown in FIGS. 1A and 1B. In FIG. 1A, a WSi.sub.x film 10 is deposited over a polysilicon film 15 to form a gate structure 20 that is part of a field effect transistor. The transistor is fabricated on a silicon substrate 5 and also includes source and drain regions 25 and 30. In FIG. 1B, a WSi.sub.x film 40 is deposited over a polysilicon layer 45 as part of a contact structure to source/drain region 50.
Many methods of forming WSi.sub.x layers exist. For example, one common technique creates a WSi.sub.x layer from a thermal reaction of monosilane (SiH.sub.4) (also referred to herein as "MS") and tungsten hexafluoride (WF.sub.6). Another method reacts dichlorosilane (SiH.sub.2 Cl.sub.2) (hereinafter referred to as "DCS") with WF.sub.6. Some DCS-based WSi.sub.x processes exhibit better step coverage, lower stress and lower fluorine content than monosilane processes and are thus preferred over MS-based processes for some applications. Despite their improved film characteristics, however, DCS-based WSi.sub.x processes are not without problems.
One problem with DCS-based processes concerns getting the film to form on the substrate. Unless certain nucleation steps are used, it is difficult to grow a WSi.sub.x film from DCS and WF.sub.6 in some applications. Another problem with DCS-based processes is the tendency for the deposited films to be tungsten-rich in the initial stages of deposition (i.e., near the interface of the WSi.sub.x film being deposited and the substrate or other layer that the WSi.sub.x film is deposited over--this area is often referred to as the "interfacial region"). This problem is illustrated in FIG. 2A, which is a graph of the ratio of silicon to tungsten in some prior art DCS WSi.sub.x films. As shown in FIG. 2A, the ratio of silicon to tungsten (line 60) can decrease significantly in some prior art DCS WSi.sub.x layers near the film interface. The formation of such an interfacial tungsten rich strata can result in delamination of the WSi.sub.x layer during annealing of the fully processed wafer in the final stages of processing. Also, voids may be created by the migration of silicon atoms from an underlying polysilicon layer to the silicon deficient WSi.sub.x layer. Such silicon migration can adversely affect device performance.
Still another problem with DCS-based WSi.sub.x films is that there can be a variance in the sheet resistance of deposited films in some instances as explained below. In depositing DCS WSi.sub.x films, it is common to process n wafers (n is between 15-25 in some processes) and then initiate a chamber clean step, which removes WSi.sub.x build-up from the interior walls of the chamber, before the next batch of n wafers are processed. It is also common to "season" the chamber after the clean step before processing the n wafers. Seasoning is done by depositing a thin layer of WSi.sub.x within the chamber without a substrate present. This seasoning layer covers contaminants and residue that may remain on chamber walls after the clean step and helps prevents these contaminants from interfering with subsequent WSi.sub.x deposition steps. An example of such a seasoning step is described in U.S. Pat. No. 5,482,749, assigned to Applied Materials.
A variance in sheet resistance occurs if, for example, during the processing of the n substrates, the deposition chamber is left idle (i.e., not processing a substrate) for a period of time. This problem is illustrated in FIG. 2B, where line 70 is the resistivity (.rho.) of WSi.sub.x films deposited over successive wafers after clean and seasoning steps. As shown in FIG. 2B, the first couple of WSi.sub.x layers deposited on substrates processed after an idle period 75 (which may occur, for example, because of a system fault) have a lower resistivity than subsequent and previously deposited layers. This problem has been referred to as the "idle effect."
One step that some manufacturers have taken to increase the Si/W ratio in the interfacial region and to reduce the idle effect is to employ a monosilane treatment step (also referred to as an "MS soak") before the WSi.sub.x nucleation and deposition steps. In the MS soak step, SiH.sub.4 introduced into the chamber to provide additional silicon for the subsequent WSi.sub.x deposition. The MS soak step is described in more detail in U.S. Pat. No. 5,817,576 and assigned to Applied Materials, the assignee of the present invention. The Ser. No. 08/314,161 application is hereby incorporated by reference for all purposes.
WSi.sub.x films deposited with such a MS soak step as a stage of the deposition process have an improved Si/W ratio in the interfacial layer and exhibit less of a variance in resistivity when the layers are deposited over substrates processed after an idle time. For example, the variance in resistivity is decreased (FIG. 2B, dashed line 72) with WSi.sub.x layers deposited after the MS soak step. Also, for applications in which the WSi.sub.x layer is deposited over an undoped or lightly-doped polysilicon layer, the Si/W ratio in films deposited with the MS soak step is improved as shown by line 62 in FIG. 2A. These WSi.sub.x films are sufficient for many applications.
While these improvements are significant, still more improvements are desirable for other applications. For example, the MS soak step is less effective at improving the Si/W ratio in WSi.sub.x films deposited over phosphorus-doped polysilicon (shown in FIG. 2A, dashed line 64). In such a case, it is believed that phosphorous from the doped polysilicon has a catalytic effect on the decomposition of subsequently introduced WF.sub.6. Thus, when WSi.sub.x films are deposited on phosphorus heavily-doped polysilicon (e.g., polysilicon having a phosphorus concentration of about 2.0.times.10.sup.20 atoms/cm.sup.3), a tungsten-rich interfacial layer is more easily formed. Also, while improved, the variance in resistivity due to the idle effect is still too much for some very small feature size processes. In these processes, the chamber was previously reseasoned after an idle period to avoid such a variance.
Accordingly, improvements in the deposition of WSi.sub.x films and in the deposition of DCS-based WSi.sub.x films in particular are desirable and are being continuously sought.